KGRKJGETMRETU895U-589TY5MIGM5JGB5SDFESFREWTGR54TY
Server : Apache/2.2.17 (Unix) mod_ssl/2.2.17 OpenSSL/0.9.8e-fips-rhel5 DAV/2 PHP/5.2.17
System : Linux localhost 2.6.18-419.el5 #1 SMP Fri Feb 24 22:47:42 UTC 2017 x86_64
User : nobody ( 99)
PHP Version : 5.2.17
Disable Function : NONE
Directory :  /usr/share/oprofile/mips/vr5500/

Upload File :
current_dir [ Writeable ] document_root [ Writeable ]

 

Current File : //usr/share/oprofile/mips/vr5500/events
#
# VR5500, VR5532 and VR7701 events
#
# Very similar to what the VR5432 provides.
#
event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed
event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction
event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Execution of store instruction
event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Execution of branch instruction
event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : Execution of floating-point instruction
event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doubleword flush to main memory
event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill
event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache miss
event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache miss
event:0xa counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch prediction miss

Anon7 - 2021