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1 : C L U q l { s W x x x ! m ) m ( @ m P W x a B k x u V | x k x x x x x x x x ' x 4 3 ; x H K O x Y e ` x h ~ s x y y w x z 4 x " / | 8 = p do_state_action <7>[nandsim] debug: read_word
<7>[nandsim] debug: device_ready
<3>[nandsim] errorr: get_state_by_command: unknown command, BUG
STATE_READY STATE_UNKNOWN STATE_CMD_READ0 STATE_CMD_READ1 STATE_CMD_PAGEPROG STATE_CMD_READOOB STATE_CMD_READSTART STATE_CMD_ERASE1 STATE_CMD_STATUS STATE_CMD_STATUS_M STATE_CMD_SEQIN STATE_CMD_READID STATE_CMD_ERASE2 STATE_CMD_RESET STATE_ADDR_PAGE STATE_ADDR_SEC STATE_ADDR_ZERO STATE_DATAIN STATE_DATAOUT STATE_DATAOUT_ID STATE_DATAOUT_STATUS STATE_DATAOUT_STATUS_M <3>[nandsim] errorr: get_state_name: unknown state, BUG
<7>[nandsim] debug: find_operation: operation found, index: %d, state: %s, nxstate %s
<7>[nandsim] debug: find_operation: no operation found, try again with state %s
<7>[nandsim] debug: find_operation: no operations found
<7>[nandsim] debug: switch_to_ready_state: switch to %s state
<7>[nandsim] debug: find_operation: BUG, operation must be known if address is input
<7>[nandsim] debug: find_operation: there is still ambiguity
<3>[nandsim] errorr: wrong bus width (%d), use only 8 or 16
<3>[nandsim] errorr: unable to allocate core structures.
<3>[nandsim] errorr: can't register NAND Simulator
<3>[nandsim] errorr: init_nandsim: nandsim is already initialized
<3>[nandsim] errorr: init_nandsim: unknown page size %u
<4>[nandsim] warnig: 16-bit flashes support wasn't tested
flash size: %u MiB
page size: %u bytes
OOB area size: %u bytes
sector size: %u KiB
pages number: %u
pages per sector: %u
bus width: %u
bits in sector size: %u
bits in page size: %u
bits in OOB size: %u
flash size with OOB: %u KiB
page address bytes: %u
sector address bytes: %u
options: %#x
<3>[nandsim] errorr: init_nandsim: unable to allocate %u bytes for flash image
<3>[nandsim] errorr: init_nandsim: unable to allocate %u bytes for the internal buffer
NAND simulator partition <3>[nandsim] errorr: scan_bbt: can't initialize the nandsim structure
<4>[nandsim] warnig: do_state_action: wrong page number (%#x)
<3>[nandsim] errorr: do_state_action: column number is too large
<7>[nandsim] debug: do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d
<7>[nandsim] log: read page %d
<7>[nandsim] log: read page %d (second half)
<7>[nandsim] log: read OOB of page %d
<3>[nandsim] errorr: do_state_action: device is write-protected, ignore sector erase
<3>[nandsim] errorr: do_state_action: wrong sector address (%#x)
<7>[nandsim] debug: do_state_action: erase sector at address %#x, off = %d
<7>[nandsim] log: erase sector %d
drivers/mtd/nand/nandsim.c WARNING: at %s:%d %s()
<4>[nandsim] warnig: do_state_action: device is write-protected, programm
<3>[nandsim] errorr: do_state_action: too few bytes were input (%d instead of %d)
<7>[nandsim] debug: do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d
<7>[nandsim] log: programm page %d
<7>[nandsim] debug: do_state_action: set internal offset to 0
<3>[nandsim] errorr: do_state_action: BUG! can't skip half of page for non-512byte page size 8x chips
<7>[nandsim] debug: do_state_action: set internal offset to %d
<7>[nandsim] debug: do_state_action: BUG! unknown action
<7>[nandsim] debug: switch_state: operation is known, switch to the next state, state: %s, nxstate: %s
<7>[nandsim] debug: switch_state: operation is unknown, try to find it
<7>[nandsim] debug: switch_state: double the column number for 16x device
<4>[nandsim] warnig: switch_state: not all bytes were processed, %d left
<7>[nandsim] debug: switch_state: operation complete, switch to STATE_READY state
<7>[nandsim] debug: switch_state: the next state is data I/O, switch, state: %s, nxstate: %s
<3>[nandsim] errorr: switch_state: BUG! unknown data state
<3>[nandsim] errorr: switch_state: BUG! unknown address state
<3>[nandsim] errorr: read_buf: chip is disabled
<3>[nandsim] errorr: read_buf: ALE or CLE pin is high
<4>[nandsim] warnig: read_buf: unexpected data output cycle, current state is %s
<3>[nandsim] errorr: read_buf: too many bytes to read
<7>[nandsim] debug: read_buf: switch to the next page (%#x)
<7>[nandsim] debug: verify_buf: the buffer is OK
<7>[nandsim] debug: verify_buf: the buffer is wrong
<3>[nandsim] errorr: write_byte: chip is disabled, ignore write
<3>[nandsim] errorr: write_byte: ALE and CLE pins are high simultaneously, ignore write
<7>[nandsim] log: reset chip
<4>[nandsim] warnig: write_byte: command (%#x) wasn't expected, expected state is %s, ignore previous states
<3>[nandsim] errorr: write_byte: unknown command %#x
<7>[nandsim] debug: command byte corresponding to %s state accepted
<7>[nandsim] debug: write_byte: operation isn't known yet, identify it
<3>[nandsim] errorr: write_byte: address (%#x) isn't expected, expected state is %s, switch to STATE_READY
<3>[nandsim] errorr: write_byte: no more address bytes expected
<7>[nandsim] debug: write_byte: address byte %#x was accepted (%d bytes input, %d expected)
<7>[nandsim] debug: address (%#x, %#x) is accepted
<3>[nandsim] errorr: write_byte: data input (%#x) isn't expected, state is %s, switch to %s
<4>[nandsim] warnig: write_byte: %u input bytes has already been accepted, ignore write
<3>[nandsim] errorr: read_byte: chip is disabled, return %#x
<3>[nandsim] errorr: read_byte: ALE or CLE pin is high, return %#x
<4>[nandsim] warnig: read_byte: unexpected data output cycle, state is %s return %#x
<7>[nandsim] debug: read_byte: return %#x status
<4>[nandsim] warnig: read_byte: no more data to output, return %#x
<7>[nandsim] debug: read_byte: read ID byte %d, total = %d
<7>[nandsim] debug: read_byte: all bytes were read
<7>[nandsim] debug: read_byte: switch to the next page (%#x)
<3>[nandsim] errorr: write_buf: data input isn't expected, state is %s, switch to STATE_READY
<3>[nandsim] errorr: write_buf: too many input bytes
<7>[nandsim] debug: write_buf: %d bytes were written
description=The NAND flash simulator author=Artem B. Bityuckiy license=GPL parm=dbg:Output debug information if not zero parm=log:Perform logging if not zero parm=do_delays:Simulate NAND delays using busy-waits if not zero parm=bus_width:Chip's bus width (8- or 16-bit) parm=input_cycle:Word input (to flash) time (nanodeconds) parm=output_cycle:Word output (from flash) time (nanodeconds) parm=erase_delay:Sector erase delay (milliseconds) parm=programm_delay:Page programm delay (microseconds parm=access_delay:Initial page access delay (microiseconds) parm=fourth_id_byte:The fourth byte returned by NAND Flash 'read ID' command parm=third_id_byte:The third byte returned by NAND Flash 'read ID' command parm=second_id_byte:The second byte returned by NAND Flash 'read ID' command (chip ID) parm=first_id_byte:The fist byte returned by NAND Flash 'read ID' command (manufaturer ID) parmtype=dbg:uint parmtype=log:uint parmtype=do_delays:uint parmtype=bus_width:uint parmtype=input_cycle:uint parmtype=output_cycle:uint parmtype=erase_delay:uint parmtype=programm_delay:uint parmtype=access_delay:uint parmtype=fourth_id_byte:uint parmtype=third_id_byte:uint parmtype=second_id_byte:uint parmtype=first_id_byte:uint srcversion=ACAE58394DF5F1FCADD02E5 depends=mtdpart,nand,nand_ids vermagic=2.6.18-308.4.1.el5 SMP mod_unload gcc-4.1 o t ( 8 o @ t H P ` o h t p x o t o t o t o t ( o 0 t 8 @ P o X t ` h x o t o t
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0 dbg log do_delays bus_width input_cycle output_cycle erase_delay programm_delay access_delay fourth_id_byte third_id_byte second_id_byte first_id_byte nandsim h q n ? OkRqdn Rm[v]O|IܵZsW m b9^`U
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# @ 3 7 G % 0 : I Z a r y nandsim.c free_nandsim ns_cleanup_module nsmtd ns_nand_read_word dbg ns_device_ready get_state_by_command get_state_name find_operation ops ns_init_module bus_width ns_hwcontrol ns_nand_read_byte ns_nand_write_buf ns_nand_read_buf ns_nand_verify_buf third_id_byte fourth_id_byte first_id_byte second_id_byte do_state_action log do_delays access_delay input_cycle erase_delay warned.11784 __func__.11787 programm_delay output_cycle switch_state ns_verify_buf __mod_description1533 __mod_author1532 __mod_license1531 __mod_dbg124 __mod_log123 __mod_do_delays122 __mod_bus_width121 __mod_input_cycle120 __mod_output_cycle119 __mod_erase_delay118 __mod_programm_delay117 __mod_access_delay116 __mod_fourth_id_byte115 __mod_third_id_byte114 __mod_second_id_byte113 __mod_first_id_byte112 __mod_dbgtype110 __param_dbg __param_str_dbg __mod_logtype109 __param_log __param_str_log __mod_do_delaystype108 __param_do_delays __param_str_do_delays __mod_bus_widthtype107 __param_bus_width __param_str_bus_width __mod_input_cycletype106 __param_input_cycle __param_str_input_cycle __mod_output_cycletype105 __param_output_cycle __param_str_output_cycle __mod_erase_delaytype104 __param_erase_delay __param_str_erase_delay __mod_programm_delaytype103 __param_programm_delay __param_str_programm_delay __mod_access_delaytype102 __param_access_delay __param_str_access_delay __mod_fourth_id_bytetype101 __param_fourth_id_byte __param_str_fourth_id_byte __mod_third_id_bytetype100 __param_third_id_byte __param_str_third_id_byte __mod_second_id_bytetype99 __param_second_id_byte __param_str_second_id_byte __mod_first_id_bytetype98 __param_first_id_byte __param_str_first_id_byte nandsim.mod.c __mod_srcversion47 __module_depends ____versions __mod_vermagic5 __udelay __this_module nand_flash_ids cleanup_module param_set_uint kfree init_module dump_stack nand_scan param_get_uint kmem_cache_alloc memcmp nand_default_bbt printk memset vfree nand_release add_mtd_partitions __const_udelay malloc_sizes vmalloc __kmalloc nandsim.ko.debug L1 .rodata.str1.1 .data .rodata .symtab .strtab .shstrtab .rela.gnu.linkonce.this_module .module_sig .gnu_debuglink .rela__param .modinfo __versions .bss .rela.text .rela.init.text .rela.exit.text @ 8 H/ 7 / 0 G X5 p= 2 = T s w Z r ]
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